1. Field of the Invention
This present invention relates to a semiconductor memory device having a gate electrode and a method of manufacturing thereof, for example, a nonvolatile semiconductor memory device with a floating gate.
2. Description of the Related Art
Hereinafter, we will explain about a conventional technique and problems thereof with accompanying drawings.
FIG. 18a shows a cross sectional view of a conventional nonvolatile semiconductor memory device. FIG. 18b shows a cross sectional view of the conventional nonvolatile semiconductor memory device perpendicular direction to the FIG. 18a. As shown in FIGS. 18a and 18b, in the conventional nonvolatile memory device, silicon oxide layers 123, 128, 131, and 133, a silicon nitride layer 134, and a poly imide resin layer 135 is laminated above memory cells 200.
It is noted that the memory cell 200 has first and second gate insulation layers 112 and 116, a floating gate that comprises first and second poly crystalline silicon layers 114 and 115, a control gate that comprises a third poly crystalline silicon layer 117, a tungsten (W) silicide layer 118, a silicon oxide layer 119 that is used as a mask layer, and diffusion layers 300. A silicon nitride layer 121 is formed so as to cover the memory cells 200. An insulation layer 122 is fulfilled among the memory cells 200.
FIGS. 19 to 24 show cross sectional views of manufacturing steps of the conventional nonvolatile semiconductor memory device. These FIGS. 19 to 24 are cross sectional views in same direction as the FIG. 18b. Hereinafter, we will explain about a method of manufacturing of the conventional nonvolatile semiconductor memory device.
As shown in FIG. 19, by using a well-known technique, memory cells are formed on a semiconductor substrate 111. Element isolation layers 113 that have a STI (Shallow Trench Isolation) structure are formed in order to isolate among element regions (See FIG. 18a).
As shown in FIG. 20, a second silicon oxide layer 120 with a thickness of, for instance, 10 nm is formed on side surfaces of first to third poly crystalline silicon layers 114, 115, and 117, a second gate insulation film 116, and a tungsten silicide layer 118 and on surface of a first gate insulation layer 112 by adding heat with, for instance, 800 degrees centigrade and nitrogen atmosphere followed by adding heat with oxidization atmosphere. Diffusion layers 300 which are used as source or drain regions are formed by using an ion implantation method. After that, a first silicon nitride layer 121 with a thickness of, for instance, 40 nm is formed on the first and second silicon oxide layers 119 and 120 by using a CVD (Chemical Vapor Deposition). The memory cells 200 are covered with the first silicon nitride layer 121. A first insulation film 122a that comprises a BPSG (Boron Phosphorous Silicate Glass) layer with a thickness of, for instance, 300 nm is formed on the first silicon nitride layer 121 by using a CVD method. After that, Heat with, for instance, 850 degrees centigrade and nitrogen atmosphere is added, thereby making the first insulation film 122a reflowed. A second insulation film 122b with a thickness of, for instance, 300 nm is deposited on the first insulation film 122a. And then, heat with, for instance, 850 degrees centigrade and nitrogen atmosphere is added, thereby making the second insulation film 122b reflowed. Hereinafter, the first and second insulation layer are called as a insulation layer 122.
As shown in FIG. 21, the insulation film 122 is flattened by using a CMP (Chemical Mechanical Polish) method so that an upper surface of the first silicon nitride layer 121 that is used as a stopper layer, is exposed. And then, Heat with, for instance, 850 degrees centigrade, 15 minutes, and nitrogen atmosphere, is added, thereby making the insulation layer 122 reflowd. Sequentially, heat with, for instance, 950 degrees centigrade and nitrogen atmosphere is added. A third silicon oxide layer 123 with a thickness of, for instance, 350 nm is deposed on the first silicon nitride layer 121 and the insulation layer 122 by using a plasma CVD method. And then, a photo resist layer (not shown) is processed to a predetermined pattern by using a photolithography technique. Predetermined portions of the third silicon oxide layer 123 and the insulation layer 122 are removed by using the photo resist layer as a mask and a RIE (Reactive Ion Etching) method. Thereby a first contact hole 124 is formed. After that, the photo resist layer is removed.
Portions of the first silicon nitride layer 121, the second silicon oxide layer 120, and the first gate insulation layer 112 that are formed at a bottom portion of the contact hole 124, are removed so as to expose an upper surface of the semiconductor substrate 111 by using the third silicon oxide layer 123 as a mask and a RIE method. And then, Formations on a side surface of the first contact hole 124 are removed. A fourth poly crystalline silicon layer 125 with, for instance, 300 nm in thickness is deposited in the first contact hole 124 and on the third silicon oxide layer 123 by using a low pressure CVD method. By using a CDE (Chemical Dry Etching) method, the fourth poly crystalline silicon layer 125 deposited on the third silicon oxide layer 123, is removed. After that, an upper portion of the fourth poly crystalline silicon layer 125 is removed so that an upper surface of the fourth poly crystalline silicon layer 125 is lower than that of the third silicon oxide layer 123. And then, heat with, for instance, 950 degrees centigrade and nitrogen atmosphere is added.
By using a photo lithography technique, a photo resist layer (not shown) is formed and processed to a predetermined pattern. The third silicon oxide layer 123, the insulation layer 122, and the first silicon nitride layer 121 are removed by using the photo resist layer with the predetermined pattern and a RIE method, thereby forming a second contact hole (not shown) on the semiconductor substrate 111 and a third contact hole (not shown) on the second poly crystalline silicon layer 115. Furthermore, simultaneously, the third silicon oxide layer 123, the first silicon nitride layer 121, the first silicon oxide layer 119, and the tungsten silicide layer 118 are removed, thereby forming a fourth contact hole (not shown) on the third poly crystalline silicon layer 117. After that, the photo resist layer of the predetermined pattern is removed.
As shown in FIG. 22, by using a photo lithography technique, a photo resist layer (not shown) is formed and processed to a predetermined pattern. The third silicon oxide layer 123 is removed by using the photo resist layer of the predetermined pattern and a RIE method. And then, the photo resist layer of the predetermined pattern is removed. Impurities are injected into desirable areas of the silicon substrate 111 by using an ion implantation method. The impurities injected into the silicon substrate 111 are activated with, for instance, 950 degrees centigrade and nitrogen atmosphere by using a RTA (Rapid Thermal Annealing) method. By using a PVD method, a titanium layer 126 with a thickness, for instance, of 30 nm is deposited. And then, heat is added with, for instance, 550 degrees centigrade, 90 minutes, and nitrogen atmosphere. Sequentially, by using a PVD method, a first tungsten layer 127 with a thickness, for instance, of 400 nm is deposited on the titanium layer 126. After that, by using a CMP method, the titanium layer 126 and the first tungsten layer 127 are flattened to such an extent that an upper surface of the third silicon oxide layer 123 is exposed. Heat is added with, for instance, 400 degrees centigrade, 30 minutes, and a mixture gas of hydrogen and nitrogen.
As shown in FIG. 23, a fourth silicon oxide layer 128 is deposited on the third silicon oxide layer 123, the titanium layer 126, the first tungsten layer 127. By using a photo lithography technique, a photo resist layer (not shown) is patterned. After that, the fourth silicon oxide layer 128 is processed by using the patterned photo resist layer as a mask, thereby, exposing a part of an upper surface of the tungsten layer 127. And then, the pattern photo resist layer is removed. A barrier metal layer (not shown) is formed on the first tungsten layer 127 and the fourth silicon oxide layer 128. A second tungsten layer 129 is deposited on the barrier metal layer. By using a CMP method, the barrier metal layer and the second tungsten layer 129 are flattened to such an extent to expose an upper surface of the fourth silicon oxide layer 128. Sequentially, a laminated layer 130 that comprises a barrier metal layer/an Al—Cu layer/a barrier metal layer (hereinafter, called as a first metal layer) is deposited. After that, by using a photo lithography technique, a photo resist layer (not shown) is patterned. By using the patterned photo resist layer as a mask, the first metal layer is processed. And then, the patterned photo resist layer is removed.
As shown in FIG. 24, by using a HDPCVD (High Density Plasma Chemical Vapor Deposition), a fifth silicon oxide layer 131 is deposited on the fourth silicon oxide layer 128 and the first metal layer 130. And then, by using a CMP method, the fifth silicon oxide layer 131 is flattened. A photo resist layer (not shown) is formed and patterned by using a photo lithography method. After that, the fifth silicon oxide layer 131 is removed by using the patterned photo resist layer as a mask, thereby espousing a part of an upper surface of the first metal layer 130. The patterned photo resist layer is removed. And then, a laminated layer (hereinafter called as a second metal layer 132) comprising a barrier metal layer and the Al—Cu layer is deposited. Sequentially, a photo resist layer (not shown) is formed on the second layer 132 and patterned by using a photo lithography method. After that, the second metal layer 132 is removed by using a patterned photo resist layer as a mask.
As shown in FIGS. 18a and 18b, by using a plasma CVD method, a sixth silicon oxide layer 133 is formed on the fifth silicon oxide layer 131 and the second metal layer 132. And then, heat is added with, for instance, 400 degrees centigrade and a mixture gas of hydrogen and nitrogen. Sequentially, by using plasma CVD method, a second silicon nitride layer 134 is formed on the fifth silicon oxide layer 131, a poly imide resin layer 135 is deposited on the second silicon nitride layer 134. Sequentially, After making an anneal with, for instance, 350 degrees centigrade, the poly imide resin layer 35, the second silicon nitride layer 134, and the sixth silicon oxide layer 133 are removed, thereby exposing a part of an upper surface of the second metal layer 132.
In the conventional memory device that is manufactured as mentioned above, a characteristic declines remarkably at a repeat test of a date reprogramming operation. Specifically, in a data retention test that is performed after the repeat test of date reprogramming operation, an alteration of “0” data (a situation where minus charged electrons are stored in the floating gate) into “1” data occurs. Therefore, it is difficult that the guaranteed number of a reprogramming test is increased. It is noted that the data retention test is defined as a test for evaluating quickly at a high temperature.